1. Field of the Invention
The present invention involves the production of electronic and mechanical devices with length scales measured in nanometers to microns. More particularly, the invention encompasses complicated electrical circuits, mechanical devices, and spatially modulated physical properties. Currently, similar devices (with larger feature sizes) are fabricated using photolithography and related processes often employed by the semiconductor industry.
2. Description of Related Art
The silicon integrated circuit industry (IC) has dominated electronics and has helped it grow to become one of the world's largest and most critical industries over the past thirty-five years. However, because of a combination of physical and economic reasons, the miniaturization that has accompanied the growth of Si IC's is reaching its limit. The present scale of devices is on the order of tenths of micrometers. New solutions are being proposed to take electronics to even smaller levels; such solutions are directed to constructing nanometer scale devices.
Prior proposed solutions to the problem of constructing nanometer scale devices have involved (1) utilization of extremely fine scale lithography using X-rays, electrons, ions, or scanning probes to define the device components; (2) direct writing of the device components by electrons, ions, or scanning probes, or (3) using a master fabricated with either process (1) or (2) to stamp the device components into a conformal layer. The major problem with (1) is the capital expense necessary to build equipment capable of fabricating devices on the nanometer lengthscale. The properties of light at these length scales require expensive optical components, as well as precision translation stages and alignment equipment. Indeed, some components necessary to produce 30 nm photolithographic structures have not even been invented yet. While (2) avoids some of these obstacles by using charged particles instead of light, the processing is inherently serial. Writing a wafer full of complex devices, each containing trillions of components, could well require many years. Process (3) is an alternative to conventional lithography, using a master stamp to imprint a pattern into a film, such as polymethyl(methacrylate). As currently practiced, however, so-called nano-imprinting is still dependent upon photo- or e-beam lithography to define the master stamp. Processes (1-3) are all limited with respect to the density of features that can be patterned. While very small structures (wires and discs), with a smallest dimension of 10 to 20 nanometers, can be patterned using various of the above techniques, it is very difficult to fabricate such small structures at a high density. The distance that separates the individual structures, known as the ‘pitch’ is typically limited to about 60 nanometers or greater. The invention described in detail below generates extremely well-defined conducting nanowires, and at densities that are well-beyond the current state-of-the-art. The invention may be utilized within the stamping motif of Process (3), however with a non-lithographically defined master that allows much smaller features to be produced.
A related, but distinctly different approach has been described by Chen & Williams (U.S. Pat. No. 6,407,443 “Nanoscale Patterning for the Formation of Extensive Wires,”). In their approach, a differentially etched silicon germanium superlattice is utilized as a stamp to produce nanoscale wire patterns in a polymer mold. Subsequent processing steps are then utilized to develop the wires into conducting materials. The subsequent processing steps, such as polymer removal, pattern etching, and metal deposition are very difficult to control at nanoscale dimensions, and so it is very difficult to transfer the atomic-level control that is realized in the superlattice structure into the final pattern of nanostructures. In the current invention, the nanowires are deposited directly onto the superlattice, and then transferred, as if they were an ink, onto the substrate, without any additional processing. This allows for the full atomic fidelity of the superlattice to be utilized. In many applications, such as those that require the mechanical or chemical properties of the nanowires, small variations in nanowire structure can lead to large variations in mechanical or chemical properties. The present invention uniquely avoids such physical properties variations in the nanowires.
There remains a need for a basic approach to form nanometer-scale devices that can be used to form more complex circuits and systems, and that scale readily and inexpensively down to nanometer scale dimensions.